Conventional mass storage integration products, such as hard disk drive systems, typically employ a conventional memory architecture as shown in FIG. 1. As shown in the figure, such an architecture employs a Synchronous Dynamic Random Access Memory (SDRAM) controller 12 located “on-board,” that is, on a semiconductor chip that includes other system components such as a hard disk drive controller, microprocessor, read/write channel and a buffer manager interface 14 with which the controller 12 is in bi-directional communication. The buffer manager interface 14 provides access to a buffer manager. A standard SDRAM 16 located “off-board,” that is, externally to the semiconductor chip on which the SDRAM controller is embodied, is in communication with the controller to allow sequential transfer of blocks of data between the SDRAM and the controller. The bandwidth of this transmission path is typically around 200 Mbytes/s. As shown in FIG. 1, the signals transmitted between standard SDRAM 16 and SDRAM controller 12 include address and data signals (Adr [11:0] and Data [15:0] or [31:0] respectively), lower and upper data mask signals (LDQM and UDQM respectively), a write enable signal (WE_N), column and row address setting signals (CAS and RAS respectively), a clock enable signal (CKE), and a clock signal (CLOCK).
One problem with this memory architecture is that the SDRAM 16 includes both direct memory access (DMA) and random memory access. This is a disadvantage in disk systems because it lowers its overall performance. Such an SDRAM has other drawbacks as well. It has relatively high power requirements, as well as a high pin count. Moreover, because of their low volume production, such SDRAM chips suffer from low availability and relatively high cost.
Accordingly, there is a need for a memory architecture for disk drive applications and the like that reduces or eliminates these shortcomings of conventional SDRAM memory architecture.